On a typical buffered dual in-line memory module (DIMM) board, a number of memory modules and a memory buffer are arranged. The memory buffer constitutes the interface between the memory controller and the memory modules spread over the board. The memory modules (as, for example, Dynamic Random Access Memories or DRAMs) require a specific and precise timing at their data, address and clock inputs. As the memory boards (DIMM boards) have a dense routing in terms of numerous wires, providing suitable and exact timing of the data and address signals, as well as the corresponding clock signals, places a high requirement on the memory buffers. If the memory buffers fail to meet the requirements, the timing at the inputs to the memory devices may be different from the timing at the corresponding outputs of the controlling devices, which may impair the overall performance of the memory systems. In order to satisfy the different timing requirements, conventional solutions shift the phase of the clock signals. For this purpose, phase locked loops (PLL) with phase mixers or delay locked loops (DLL) are used to optimize the phase relationship of a clock signal with regard to a data signal. However, PLLs and DLLs consume a considerable amount of chip area. Further, as data throughput of the memory buffering devices increases, the power consumption and the heat produced in the memory buffering devices, in particular in the DLLs and PLLs, creates problems.